add asyn_fifo.v
This repository is used to introduce to some projects or modules bases on the mainly lanuage–verilog.
git config –global credential.helper store //then git push again,and next will not need to input the username and password. =======
[1] https://github.com/sin-x/FPGA/tree/master
IC/FPGA Project Module Code.
©Copyright 2023 CCF 开源发展委员会 Powered by Trustie& IntelliDE 京ICP备13000930号
IC_FPGA_projects
This repository is used to introduce to some projects or modules bases on the mainly lanuage–verilog.
1 slove the every time git push need to input the username and password.
git config –global credential.helper store //then git push again,and next will not need to input the username and password. =======
2 Useful references
[1] https://github.com/sin-x/FPGA/tree/master