[Triton] Fea/warp layout broadcast from upstream triton (#1150)

[Analysis] Backport layout prerequisites for Triton #11646

Add the input/output basis-mask helpers and update packed transposition
selectors to the upstream algorithm preceding #11646. Keep selector
ordering correct when low register bits participate in multiple factors,
and fold remaining low-bit register permutations into pre-shuffle selectors.
The selector implementation comes from upstream af85fc304db5, the parent
of 2074a1b8a5cd (Triton #11646). The basis-mask helpers are backported from
the same upstream API with compatibility for FlagTree’s LinearLayout.
This commit keeps the existing conversion structure and lowering interfaces.
Validation on H20: NVIDIA/AMD build, pre-commit, five C++ test groups,
focused conversion IR tests, and existing warp-local GPU conversion tests.

[BACKEND] Backport broadcast-local warp shuffles from Triton #11646

Allow layout conversions to read broadcast copies in the current warp or
CTA, carrying warp/block-dependent owner lane bits into the shuffle map.
Extend mixed transpositions to support one-sided exchanges and retain the
existing mixedTranspositions.size() < 2 cost check.
Backport upstream 2074a1b8a5cd283ce584f8ebca825c4f0b215fc1:
https://github.com/triton-lang/triton/pull/11646
Keep the required FlagTree compatibility changes with the feature so this
commit builds independently: retain tensor-type analysis interfaces,
explicit zero padding for the older resizeInDim API, existing register
packing/broadcast helpers, and the existing shared-memory fallback.
Adapt both common lowering and AMD permlane selection to the new fields.
Backport permutation/identity checks as local analysis helpers instead of
expanding FlagTree’s public layout APIs. Upstream force_warp_shuffle and
GenericLinearEncoding are outside this backport.
Include applicable upstream IR coverage and updated duplication-reduction
expectations. Validation: NVIDIA/AMD build, pre-commit, five C++ test groups,
and focused NVIDIA/AMD conversion IR tests.

[Test] Cover broadcast-local layout shuffles in FlagTree

Add the 16x1 pointer layout regression from FlagTree #1047 for NVIDIA and
AMD wave64. Check that conversion emits two 32-bit shuffles without shared
memory or a barrier. Add layout-unit coverage for local broadcast copies,
including partially broadcast warp bits and CTA locality.
Adapt and extend the upstream layout pairs into GPU tests covering forward
and reverse conversions, multiple element widths, runtime pointers, owner
lanes, packed exchanges, and register selection.
Validation on H20: pre-commit, five C++ test groups, five focused IR files,
and 236 GPU cases passed (244 existing cases skipped). All 88 added GPU
cases passed. AMD wave64 is validated by compilation, not AMD hardware.

[AMD][Metax] Preserve legacy layout decomposition in mixed builds

Metax builds the shared AMD permlane lowering against its own pre-#11646
analysis header. Reading regBit and dstLane from that older decomposition
breaks compilation in FlagTree #1150.
Use the existing USE_MACA condition to select Metax’s pLane/transposition
representation; other builds continue using shuffleMap/regBit/dstLane.
Keep the original Metax shuffle gate and analysis implementation unchanged.
Annotate each compatibility change with Triton #11646 and FlagTree #1150.
Validation on H20:

Reproduced the missing-member errors using the actual Metax analysis header;
the same AMD translation unit passes syntax checking after the fix.
NVIDIA/AMD build and pre-commit passed.
All 24 existing gfx950 permlane cases produce identical LLVM IR before
and after the fix.
Five focused conversion IR files and five C++ test groups passed.
All 88 broadcast-layout GPU regression cases passed.

The complete Metax SDK build and device tests remain for platform CI.

[CORE] Isolate layout shuffle backport with the FlagTree feature macro

Define FLAGTREE_SAME_WARP_LAYOUT_SHUFFLE directly in the default
NVIDIA/AMD configuration, following the existing FlagTree feature macros.
Wrap all native source differences in the layout backport, including its
prerequisites and C++ regression coverage, in matching ifdef/else/endif
blocks. Preserve the original declarations, analysis, selectors, and
lowering in the disabled branches. Select the legacy AMD interface when
the feature is absent, so Metax does not depend on the new decomposition.
Keep this feature independent of the TLE macro.
Validation on H20:

NVIDIA/AMD build, pre-commit, five C++ groups, five IR files, and all
88 broadcast-layout GPU cases passed.
All 24 gfx950 permlane LLVM IR outputs match the original backport.
Disabled branches restore every pre-backport nonblank source line.
Eight CMake backend configurations passed.
All five affected translation units pass syntax checking with the
feature disabled and with it enabled without TLE.
Shared AMD lowering passes syntax checking with the actual Metax
analysis header and the feature disabled.


[CORE] Match feature guard spacing to the original source

Remove blank lines next to conditional branch boundaries and preserve
the original source spacing outside each guard. Drop empty else branches
from the three blocks containing only new code.
Validation: pre-commit and git diff –check passed. All 11 feature guards
match the original boundary spacing; enabled and disabled code tokens
are unchanged across all seven affected native source files.

Co-authored-by: zhzhcookie zhengyang@baai.ac.cn