Huizhe Wang

Merge branch ‘pcie-ssd’ into ‘master’
Pcie ssd
See merge request pard/labeled-RISC-V!239

5年前7072次提交

.githubAdd Issue/PR Template based off of Chisel/FIRRTL (#1502)7年前
bootromchange DRAM base6年前
csrcMerge branch 'master' into merge7年前
emulatorMerge commit 'a05728c4fab84a13585e14ac684b47c875b17b57' into boom6年前
fpgaMerge branch 'pcie-ssd' into 'master'5年前
macrosValName: 'lazy val' now also counts for providing a name7年前
projectBump firrtl, json4s, and sbt (#1739)6年前
regressionChange riscv-tools install rule so checkout is an order-requ rather than dependency. This is to6年前
scriptsMerge remote-tracking branch 'shinezyy/boom' into bump-rocket6年前
srclvna,LvNAConfigs: add more interrupts for pcie6年前
vsimMerge branch 'upstream' into merge-upstream6年前
.gitignoreAdd two types of debug facilities6年前
.gitmodulesMerge commit 'a05728c4fab84a13585e14ac684b47c875b17b57' into boom6年前
.travis.ymlBump verilator to v4.008 (#1762)6年前
LICENSE.Berkeleyscripts: two scripts to determine copyright holder of files8年前
LICENSE.SiFiveUpdate LICENSE.SiFive (#618)8年前
LICENSE.jtagAdd ucb-art/chisel-jtag (#612)8年前
MakefragAdded makefile rules for bootrom image.6年前
README-rocketchip.mdUpdate readme6年前
README.mdUpdate readme6年前
README_LvNA.mdupdate doc7年前
README_TRAVIS.mdUpdate README_TRAVIS.md8年前
build.sbtBump firrtl, json4s, and sbt (#1739)6年前
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riscv-tools.hashbumping riscv-tools6年前
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chisel3@9a0ce2272cBump chisel36年前
firrtl@2272044c6aBump firrtl6年前
hardfloat@45f5ae171abump hardfloat for scala 2.11.12 (#1216)7年前
torture@77195ab12aMerge with Head8年前

README.md

Labeled RISC-V based on Rocketchip

We build our labeled RISC-V prototype based on rocketchip.

Quick start guide for labeled RISC-V,
Original Rocketchip README.

关于

基于精简指令集（RISC）原则的开源指令集架构，用于允许任何人设计、制造和销售RISC-V芯片和软件。

scala tcl python

README.md

16.5 MB

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