Update the Chisel version to 3.6.1
An almost empty chisel project (and adder) as a starting point for hardware design.
To generate Verilog code for the adder execute:
make
Run the tests with:
make test
Cleanup the repository with:
make clean
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chisel-empty
An almost empty chisel project (and adder) as a starting point for hardware design.
To generate Verilog code for the adder execute:
Run the tests with:
Cleanup the repository with: