feat(fpga_diff): add AXI4 and H2C AXI stream ports (#128)

Expose the FpgaDiffTop memory path as standard difftest AXI4 ports in the FPGA wrappers. Add the XDMA H2C AXI stream path for workload loading, including the H2C reset CDC and pcie clock domain AXIS width/clock conversion in the XDMA block design.

Rename difftest AXI stream wrapper ports to the tvalid/tdata style so Vivado can recognize the interface.