feat(fpga_diff): support BOOM with shared AXI width (#192)

• Add the BOOM SimTop wrapper, connecting memory AXI to DDR and MMIO AXI to the existing UART16550 at 0x310b0000.
• Define CPU-side AXI data/address widths once in shared Tcl: BOOM/NutShell use 64/33, XiangShan targets use 256/40. Vivado uses these variables for RTL macros and the SOC_M_AXI BD data width.
• Add BOOM selection/defines. UVHS filelist generation reads the same Tcl width definitions.
• Correct the unmatched Tcl log-string quote and missing Verilog macro expansion prefixes from the previous width conversion.