Kamimiao

fpga_diff: support difftest axi-stream interface (#58)
This change adds support for the standard Difftest AXI-Stream interface.
Meanwhile, the Difftest2AXI module is now generated directly inside SimTop
using Chisel, removing the need for manually instantiated wrapper and 
wiring.

10天前315次提交

busbus: add transaction parser scripts for tilelink database2年前
fpgaextract_spec.py support ci log (#39)8个月前
fpga_difffpga_diff: support difftest axi-stream interface (#58)10天前
githubfeat(ci-robot): add manual selection of the branch to monitor17天前
licensecomplete add_license func4年前
logviewerlogparser: remove common prefix in module names4年前
perffeat(xsautorun): add simfrontend config (#62)15天前
regfile_replace Add the script to generate the needed regfile automatically.4年前
simulationsupport nanhu palladium project3年前
timingtiming: support dedup in analyze timing3年前
verilogverilog,parse: add comments to files3年前
xs_kmh_fpgaFix update_core_flist (#52)2个月前
xs_nanhu_fpgaUpdate nanhu's xdma bd tcl to support 2 PCIe RC (#37)9个月前
.gitignorefix the gitignore setting issue that cause the xs_kmh_fpga folder misssing files (#40)8个月前
README.mdUpdate to env scripts4年前
requirements.txtxsautorun: fix is_epyc() in server.py; read server info with sshconf and glances (#28)1年前

README.md

env-scripts

Scripts for XS

关于

python scala html

README.md

4.3 MB

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