Out-of-order RISC-V (RV32/RV64 IMAC_Zicsr_Zifencei) processor core with register renaming, ROB, and reservation stations. The RTL is described by SystemVerilog with Chisel (Scala) used only for decoder generation. Features Sv32 virtual memory (MMU/TLB), LR/SC + AMO atomics, compressed instructions (RVC), and boots Linux v6.18 via OpenSBI. Supports configurable RV32 and RV64 modes via compile-time switch.
Candidate ip core name: raptor-falcon-0.1.0 (rf-0.1.0).
Suggest install tmux for better terminal management. surfer for wave viewer. colima for Linux container.
# One-line setup (installs all dependencies)
make setup
# Optional: install espresso if you need
wget https://github.com/chipsalliance/espresso/releases/download/v2.4/arm64-apple-macos11-espresso
Quick Start
All commands run from the project root. (No need to source env.sh - the Makefile exports all environment variables automatically.)
# Show all available targets
make help
1. NEMU (Software Emulator)
# Configure, build and run NEMU (riscv32)
make run-nemu32
# Or step by step
make config-nemu32 # configure (riscv32_defconfig)
make build-nemu32 # build
make run-nemu32 # run
# Interactive menuconfig
make menuconfig-nemu32
2. NPC Simulation (Verilator)
# Full pipeline: generate RTL -> configure -> build -> run
make sim-npc32
# Or step by step
make verilog # Chisel -> SystemVerilog
make config-npc32 # configure (o2_defconfig)
make build-npc32 # build Verilator simulator
make run-npc32 # run simulation
# Run with args
make run-npc32 ARGS="-b -n" # -b: batch mode [default], -n: no wave trace
make run-npc32 IMG=path/to.bin # load custom image
# Interactive menuconfig
make menuconfig-npc32
RV64 Mode
The processor supports RV64 via a compile-time switch (-DYSYX_RV64). Switching between RV32 and RV64 automatically invalidates the build cache, no manual make clean needed.
# Build and run in RV64 mode (convenience targets)
make build-npc64
make run-npc64 ARGS="-b -n"
# Or explicitly pass VFLAGS
make run-npc32 VFLAGS="-DYSYX_RV64" ARGS="-b -n"
# Lint in RV64 mode
make lint-npc64
3. Benchmarks
# Run on NPC (riscv32e-npc)
make coremark-npc32 ARGS="-b -n"
make microbench-npc32 ARGS="-b -n"
# Run on NPC with difftest (vs NEMU reference)
make coremark-npc32-difftest ARGS="-b -n"
make microbench-npc32-difftest ARGS="-b -n"
# Run on ysyxSoC
make coremark-ysyxsoc ARGS="-b -n"
make microbench-ysyxsoc ARGS="-b -n"
# Run on NEMU (riscv32-nemu)
make coremark-nemu32 ARGS="-b -n"
make microbench-nemu32 ARGS="-b -n"
4. Nanos-lite OS
# Run nanos-lite on NEMU
make nanos-nemu32
# Run nanos-lite on NPC
make nanos-npc32
5. Linux Kernel
# Boot Linux on NEMU (requires OpenSBI payload built first)
make linux-boot-nemu32
# Boot Linux on NPC
make linux-boot-npc32
# Boot Linux on NPC with difftest (vs NEMU reference)
make linux-boot-npc32-difftest
# See detailed instructions
# docs/linux_kernel.md, linux/README.md
6. FPGA
# Synthesize for Gowin Tang Nano 20K
make fpga-syn
# Place and route
make fpga-pnr
# See fpga/gowin-tang-nano-20k/README.md for details
7. Utilities
# Pack all SV into one file
make pack
# Lint RTL
make lint
# Static timing analysis
make sta
# Clean all build artifacts
make clean
Build and Run (Manual)
The following commands are equivalent to the make targets above,
useful if you need finer-grained control.
# 0. environment variables at project root directory
source ./env.sh
# 1. build and run NEMU
cd $NEMU_HOME && make riscv32_defconfig && make && make run
cd $NEMU_HOME && make riscv32_linux_defconfig && make && make run
# 2. build and run NPC
cd $YSYX_HOME/rtl_scala && make verilog
cd $NSIM_HOME && make o2_defconfig && make && make run
cd $NSIM_HOME && make o2linux_defconfig && make && make run
cd $NSIM_HOME && make menuconfig && make ARCH=riscv32e-npc run
# 3. build and run the program you want
## n. running nanos-lite on nemu
cd $NAVY_HOME && make ISA=$ISA fsimg
cd $NAVY_HOME/apps/menu && make ISA=$ISA install
cd $YSYX_HOME/nanos-lite && make ARCH=$ISA-nemu update run
cd $YSYX_HOME/nanos-lite && make ARCH=$ISA-nemu run
## n.vme running nanos-lite on nemu with VME
cd $YSYX_HOME/nanos-lite && make ARCH=$ISA-nemu update run ARGS="-b" VME=1
## n+1. running busybox on nemu (Linux required)
cd $NAVY_HOME/apps/busybox && colima ssh # login to Linux container
make ARCH=riscv32-nemu install
## 2n. running microbench/coremark on npc
cd $YSYX_HOME/am-kernels/benchmarks/coremark_eembc && \
make ARCH=riscv32e-npc run ARGS="-b -n"
cd $YSYX_HOME/am-kernels/benchmarks/microbench && \
make ARCH=riscv32e-npc run ARGS="-b -n"
# ARGS="-b -n" is optional, -b is for batch mode [default], -n is for no wave trace
## fpga. running on gowin-tang-nano-20k
### follow `fpga/gowin-tang-nano-20k/README.md`
## package all sv files into one
cd nsim && make pack
Raptor Project
Out-of-order RISC-V (RV32/RV64 IMAC_Zicsr_Zifencei) processor core with register renaming, ROB, and reservation stations. The RTL is described by
SystemVerilogwithChisel(Scala) used only for decoder generation. Features Sv32 virtual memory (MMU/TLB), LR/SC + AMO atomics, compressed instructions (RVC), and boots Linux v6.18 via OpenSBI. Supports configurable RV32 and RV64 modes via compile-time switch.Candidate ip core name:
raptor-falcon-0.1.0(rf-0.1.0).Microarchitecture
Core Documentation
Build Setup
Suggest install
tmuxfor better terminal management.surferfor wave viewer.colimafor Linux container.Quick Start
All commands run from the project root. (No need to
source env.sh- the Makefile exports all environment variables automatically.)1. NEMU (Software Emulator)
2. NPC Simulation (Verilator)
RV64 Mode
The processor supports RV64 via a compile-time switch (
-DYSYX_RV64). Switching between RV32 and RV64 automatically invalidates the build cache, no manualmake cleanneeded.3. Benchmarks
4. Nanos-lite OS
5. Linux Kernel
6. FPGA
7. Utilities
Build and Run (Manual)
Run OpenSBI & Linux Kernel
See Linux Kernel
Reference